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Espressif Systems /ESP32-S3-ULP /RTC_I2C /INT_CLR

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Interpret as INT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SLAVE_TRAN_COMP_INT_CLR)SLAVE_TRAN_COMP_INT_CLR 0 (ARBITRATION_LOST_INT_CLR)ARBITRATION_LOST_INT_CLR 0 (MASTER_TRAN_COMP_INT_CLR)MASTER_TRAN_COMP_INT_CLR 0 (TRANS_COMPLETE_INT_CLR)TRANS_COMPLETE_INT_CLR 0 (TIME_OUT_INT_CLR)TIME_OUT_INT_CLR 0 (ACK_ERR_INT_CLR)ACK_ERR_INT_CLR 0 (RX_DATA_INT_CLR)RX_DATA_INT_CLR 0 (TX_DATA_INT_CLR)TX_DATA_INT_CLR 0 (DETECT_START_INT_CLR)DETECT_START_INT_CLR

Description

interrupt clear register

Fields

SLAVE_TRAN_COMP_INT_CLR

clear slave transit complete interrupt
ARBITRATION_LOST_INT_CLR

clear arbitration lost interrupt
MASTER_TRAN_COMP_INT_CLR

clear master transit complete interrupt
TRANS_COMPLETE_INT_CLR

clear transit complete interrupt
TIME_OUT_INT_CLR

clear time out interrupt
ACK_ERR_INT_CLR

clear ack error interrupt
RX_DATA_INT_CLR

clear receive data interrupt
TX_DATA_INT_CLR

clear transit load data complete interrupt
DETECT_START_INT_CLR

clear detect start interrupt

Links

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Register License

Copyright 2023 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data